1. Field of Invention
The present invention pertains to a receiving apparatus which may be used in Bluetooth and/or other such wireless communication equipment carrying out transmitting and/or receiving.
2. Conventional Art
Conventional proposals for receiving apparatuses capable of receiving wireless signals modulated by means of FSK (frequency shift keying) or the like include apparatuses having the circuit structure shown in FIG. 6, as disclosed for example at Japanese Patent Application Publication Kokai No. 2002-290178 (2002).
At the receiving apparatus shown in FIG. 6, a received RF (radio frequency) signal input from antenna 301 is amplified by LNA (low noise amplifier) 302 and is thereafter, at mixer 303, mixed with a local signal output from VCO (voltage-controlled oscillator) 304 and is converted into an IF (intermediate frequency) signal. The IF signal produced as a result of conversion is input at variable gain amplifier 305. At such time, variable gain amplifier 305 is set to its maximum gain.
The output signal from variable gain amplifier 305 branches into two output signal lines, one of which is input at level detection circuit 306. Level detection circuit 306 outputs a DC (direct current) voltage corresponding to the level of the signal output from variable gain amplifier 305. The signal output from level detection circuit 306 is input at comparing circuit 307.
Comparing circuit 307 compares the DC voltage output by level detection circuit 306 with a reference DC voltage, outputting an output signal when the DC voltage output by level detection circuit 306 is higher than the reference voltage (which signal is inverted relative to the output signal produced by comparing circuit 307 when the DC voltage output by level detection circuit 306 is lower than the reference voltage), for decreasing the gain of variable gain amplifier 305. As a result, an IF signal can be obtained without saturation of the output level of variable gain amplifier 305, even under conditions of forced input of the signal received from antenna 301.
The other of the two output signal lines from variable gain amplifier 305 is acted upon by limiter amplifier 308 and the signal output therefrom is made to possess constant output amplitude. The output from limiter amplifier 308 branches into two lines, one of which is input at demodulating mixer 310. The other output line from limiter amplifier 308 is input at phase circuit 309 and is shifted in phase by 90°.
As a result of multiplication, at demodulating mixer 310, of the output from this phase circuit 309 and the output from this limiter amplifier 308, a demodulated analog signal is output from demodulating mixer 310. While the demodulated analog signal contains high-frequency signal and carrier components produced as a result of multiplication, such high-frequency signal and carrier components are removed by means of LPF (low pass filter) 311. The demodulated analog output from LPF 311 is input at binarizing circuit 312.
Binarizing circuit 312 comprises slice level detection circuit 313 and comparing circuit 314. Slice level detection circuit 313 generates an optimum slice level in correspondence to the signal input thereto. Comparing circuit 314 compares the output from slice level detection circuit 313 and the output from LPF 311, performing binarization and outputting a binary signal.
Next, specific examples of binarizing circuits which may be employed in receiving apparatuses are shown in FIGS. 7 and 8.
FIG. 7 is an example of a binarizing circuit making use of demodulated signal minimum and maximum hold values.
At binarizing circuit 401 shown in FIG. 7, the demodulated signal is respectively input at minimum value detection circuit 404 and at maximum value detection circuit 403 of slice level detection circuit 402, the peak minimum value thereof being stored at minimum value detection circuit 404 and the peak maximum value thereof being stored at maximum value detection circuit 403. This peak minimum value and this peak maximum value are added together at adding circuit 405, the value produced as a result of this operation being halved at amplifier 406.
As a result of the foregoing operations, slice level detection circuit 402 outputs [(peak minimum value+peak maximum value)/2], this output being input at comparing circuit 407. Comparing circuit 407 carries out binarization by comparing the magnitude of the demodulated signal and the magnitude of the output from slice level detection circuit 402.
At binarizing circuit 501 shown in FIG. 8, the demodulated signal is input at adding circuit 502. The output from adding circuit 502 branches into two lines, the signal from one of which is input at offset canceler circuit 503. Offset canceler circuit 503 outputs a signal in accordance with the input/output characteristics of Formula (1).
                    output        =                  {                                                                                          -                    input                                    +                  A                                                                              (                                      input                    >                    A                                    )                                                                                                                                                                  0                                                              (                                                            -                      A                                        ≤                    input                    ≤                    A                                    )                                                                              (                                      A                    ⁢                                          :                                        ⁢                                                                                  ⁢                    cutoff                    ⁢                                                                                  ⁢                    value                    ⁢                                                                                  ⁢                                          (                      constant                      )                                                        )                                                                                                                          -                    input                                    -                  A                                                                              (                                      input                    <                                          -                      A                                                        )                                                                                                                                                                      (        1        )            The output from offset canceler circuit 503 is input at integrating circuit 504. The output from integrating circuit 504 is input at adding circuit 502 and is added to the original demodulated signal.
As a result of the foregoing operations, the output from adding circuit 502 is converted into a signal which is centered on the value “0”. The other signal line from adding circuit 502 is input at sign determining circuit 505, the sign of the signal input thereto being used to carry out binarization.
A receiving apparatus having the circuit structure shown in FIG. 6 permits attainment of wide input dynamic range. Furthermore, with such a receiving apparatus, it is possible by employing a binarizing circuit of structure as shown in FIG. 7 and/or 8 to accurately carry out binarization while still being able to accommodate sudden changes in DC level.
However, with a receiving apparatus of circuit structure such as is shown in FIG. 6, because the gain of the variable gain amplifier is switched discontinuously, noise is produced in the output of the variable gain amplifier during switching of the gain thereof. This noise will also affect the limiter amplifier which is downstream therefrom, as well as components downstream from the limiter amplifier. That is, presence of noise in the output from the variable gain amplifier will cause the slice level detection circuit to output a slice level which is different from the slice level that it would otherwise output, causing deterioration in the BER (bit error rate).
For example, taking the case of a receiving apparatus provided with the binarizing circuit of FIG. 7, as indicated in the output waveform diagram of FIG. 9, presence of noise due to switching of gain will cause the output (slice level) from amplifier 406 of binarizing circuit 401 to, under the influence of such noise, differ from what it would otherwise be, producing errors.
Or taking the case of a receiving apparatus provided with the binarizing circuit of FIG. 8, as indicated in the output waveform diagram of FIG. 10, presence of noise due to switching of gain will cause the output (adding circuit 502 output) from offset canceler circuit 503 of binarizing circuit 501 to, under the influence of such noise, differ from what it would otherwise be, producing errors.